XCENA Raises $135M to Tackle AI Memory Bottlenecks

AI infrastructure startup XCENA has raised $135 million in a Series B funding round, pushing the company’s valuation to $570 million [1]. The startup, which focuses on mitigating memory bottlenecks in generative AI systems, has now secured a total of $185 million in funding to date [1].

Key takeaways

• The Series B round was co-led by Atinum Investment and IMM Investment, with participation from several other institutional backers [1, 2].
• XCENA’s flagship product, the MX1, is a computational memory controller designed to perform data tasks closer to DRAM to bypass CPUs [1, 2].
• The company claims its architecture could potentially allow workloads that currently require 10 servers to run on a single server [1].
• Founded in 2022 by former Samsung and SK Hynix executives, the startup plans to begin mass production via Samsung’s foundry by the end of 2026 [1, 3].

Addressing the AI Data Relay Race

XCENA was established in 2022 by CEO Jin Kim, CTO Dohun Kim, and CPO Harry Juhyun Kim, all of whom previously held executive roles at memory chip giants Samsung and SK Hynix [1]. The company is targeting the inefficiency of modern AI servers, where data must repeatedly travel between memory, CPUs, and GPUs during the inference process [1, 3]. This constant movement consumes significant power and time, creating a "relay race" that limits performance [3].

The MX1 chip functions as a computational memory controller that connects to CPUs via the CXL high-speed interface [1, 3]. By performing routine operations—such as preprocessing, data caching, and KV cache management—directly inside the memory module, the device aims to reduce the processing overhead that typically burdens CPUs [1, 2]. The MX1 integrates up to two terabytes of DRAM with thousands of RISC-V-based CPU cores, allowing it to handle complex data structures like vector databases and KV caches without offloading them to slower external memory [2].

Production Plans and Market Positioning

While the MX1 remains in the prototype stage, XCENA has established a manufacturing partnership with Samsung [1, 3]. The company plans to utilize Samsung’s four-nanometer chip manufacturing process to begin mass production by the end of 2026, with commercial revenue expected to follow in 2027 [2, 3]. To support adoption, XCENA provides developers with application programming interfaces (APIs) designed to port AI workloads to the MX1 without requiring major code changes [2].

Why it matters

As the AI industry shifts its focus from model training to large-scale inference, memory efficiency has become a critical constraint for hyperscalers [1, 3]. XCENA is positioning itself against competitors like Marvell and Astera Labs in the emerging market for memory-centric AI infrastructure [1]. The company intends to use its new capital to accelerate go-to-market efforts, develop additional computational memory products, and form partnerships with major industry players [2]. With global spending on high-bandwidth memory (HBM) reaching $54.6 billion in 2026, XCENA is betting that infrastructure providers will prioritize memory-centric solutions to lower the soaring costs of running generative AI systems [1, 3].