Viavi launches PCIe 6.0 testing platform at Flash Memory Summit

Viavi Solutions announced that its new Xgig PCIe 6.0 protocol analysis testing platform will be demonstrated at the Flash Memory Summit on August 8‑10, offering analysts, exercisers and interposers capable of capturing 64 GT/s PCIe 6.0 traces on existing PCIe 5.0 equipment【2】. The move gives hardware designers early‑stage validation tools as the industry prepares for the first PCIe 6.0 products projected for 2025.

Platform capabilities and timing

The Xgig PCIe 6.0 suite adds analyzers, exercisers and interposers to Viavi’s Xgig family, extending the life of current PCIe 5.0 test equipment by allowing 64 GT/s trace capture without new hardware purchases【2】. Software features such as Trace Control, Expert, Serialytics and MLTT streamline data interpretation, while full‑stack analysis now covers NVMe and CXL protocols. A notable addition is the Link Training and Status State Machine (LTSSM) override, which lets users generate corner‑case states to uncover hidden issues—critical as PCIe 6.0’s higher speeds raise thermal and signal‑integrity challenges.

PCIe 6.0 doubles the bandwidth of the preceding PCIe 5.0 specification, moving from 32 GT/s to 64 GT/s, which translates to 256 GB/s on an x16 graphics‑card link【1】. Although the specification was finalized in 2022, no commercial PCIe 6.0 products have shipped yet; the first integrator’s list is projected for 2025【1】. Viavi’s platform therefore targets the R&D phase, giving chipmakers and system integrators a way to validate designs ahead of silicon availability.

Industry context

The announcement arrives as the PCI‑SIG continues to outline future roadmaps, having already announced PCIe 7.0 for 2027 and begun work on PCIe 8.0【1】. By providing a testing solution that can also capture PCIe 6.0 traces on existing PCIe 5.0 hardware, Viavi helps customers defer capital expenditures while the ecosystem matures. The broader data‑center, hyperscale, AI/ML and quantum‑computing markets, which rely on ever‑faster interconnects, stand to benefit from early detection of performance bottlenecks.

What to watch

• PCI‑SIG integrator list – expected release in 2025, will confirm the first commercial PCIe 6.0 components.
• Subsequent product announcements – Intel’s Panther Lake and other early‑generation PCIe 6.0 CPUs/chipsets slated for late‑2025.
• Thermal management solutions – developments in active cooling or link‑throttling mechanisms as designers address heat concerns highlighted by prior PCIe 5.0 SSD implementations【1】.

Viavi’s PCIe 6.0 testing platform underscores the growing demand for high‑speed validation tools ahead of the first silicon shipments, while also highlighting the industry’s cautious pacing as it balances performance gains against emerging thermal and signal‑integrity challenges.