# Intel patent unveils ZAM memory architecture aiming to halve AI power

**Published:** 2026-07-07T15:50:36.506Z  
**Topic:** Layer 2 Scaling  
**Sentiment:** neutral  
**Publisher:** TrendWatcher — https://www.trendwatcher.in/article/63b05992-af55-4b52-8689-2f2b743e976d

Intel’s new Z‑Angle Memory (ZAM) patent promises up to 50% lower power than HBM4, targeting 2029 commercialization to cut AI data‑center costs.

Intel’s recently filed patent describes a “Z‑Angle Memory” (ZAM) architecture that could cut AI‑center power consumption by roughly half compared with current HBM4 solutions, a move that directly tackles the supply‑chain bottleneck created by reliance on Korean memory vendors [1].  

| At a glance | |
|---|---|
| Power reduction claim | ~50% vs. HBM4 |
| Target commercialization | FY 2029 |
| Prototype launch | FY 2027 |
| Supply‑risk motive | Reduce dependence on Samsung, SK Hynix, Micron |

## Architecture shift and why it matters  
The ZAM design replaces the dense “honeycomb” of thousands of through‑silicon vias (TSVs) used in HBM stacks with a single central “trunk” that carries power and signals. Intel says this “Via‑in‑One” channel can increase effective DRAM storage area by more than 30% and shorten signal paths, which together lower latency and improve mechanical integrity [1]. By eliminating the TSV mesh, the architecture also acts as a vertical heat pipe, allowing heat to exit more efficiently and driving the projected 50% power cut.  

## Timeline, partners and market context  
SoftBank’s SAIMEMORY subsidiary, created in December 2024, is the corporate vehicle for ZAM development, with a prototype slated for fiscal 2027 and full commercialization aimed for fiscal 2029 [1]. Intel’s involvement is framed as a strategic hedge against the “single‑path” dependence on HBM, which currently concentrates capacity in three Korean firms and has driven DRAM prices up more than 200% since early 2025 [2]. The patent’s multi‑assembly, modular stacking approach is positioned as a de‑HBM path that could free AI servers from the cadence of Korean memory‑vendor capex cycles [1].

| Metric | Value |
|---|---|
| Expected power use vs. HBM4 | ~50% |
| Effective storage increase | >30% |
| Prototype target year | FY 2027 |
| Commercial launch target year | FY 2029 |

## What to watch  
- **Prototype rollout** – SAIMEMORY’s FY 2027 prototype debut will be the first concrete test of ZAM’s claimed power and density gains.  
- **Patent citations** – Follow subsequent filings that reference the ZAM architecture, indicating broader industry adoption or licensing activity.  
- **AI‑center power metrics** – Monitor power‑per‑bit reports from major data‑center operators for any shift toward the 50% reduction benchmark.  

If ZAM delivers on its promises, it could reshape AI infrastructure by decoupling compute growth from the limited HBM supply chain, forcing a re‑evaluation of memory‑centric design assumptions that have dominated the sector for over a decade. The open question remains whether the architecture can scale to the volumes and yields required for mainstream data‑center deployment.

## Sources
1. Tspasemiconductor — [Can ZAM Replace HBM? Intel and SoftBank Push Radical Memory Architecture](https://tspasemiconductor.substack.com/p/can-zam-replace-hbm-intel-and-softbank)
2. Wikipedia — [High Bandwidth Memory - Wikipedia](https://en.wikipedia.org/wiki/High_Bandwidth_Memory)

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Cite as: TrendWatcher, "Intel patent unveils ZAM memory architecture aiming to halve AI power", https://www.trendwatcher.in/article/63b05992-af55-4b52-8689-2f2b743e976d