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New 150 °C atomic layer deposition method grows epitaxial tellurium on van der Waals substrates, opening a path for AI chips and ultra‑low‑power devices.
A new atomic layer deposition (ALD) process developed by KAIST researchers can grow crystal‑aligned tellurium (Te) films at just 150 °C, preserving delicate van der Waals interfaces while delivering high‑quality semiconductor layers—an advance that could accelerate next‑generation AI and optoelectronic hardware [1].
| At a glance | |
|---|---|
| Temperature | 150 °C |
| Materials | Tellurium on WSe₂, MoS₂, ReSe₂, mica |
| Technique | Diffusion‑steered epitaxial ALD |
| Catalyst | Low‑temperature growth without interface damage |
The team replaced random nucleation with a diffusion‑steered approach: Te‑containing precursor molecules migrate across the substrate until they reach energetically favorable sites, then lock into place, producing a uniformly aligned crystal lattice that mirrors the underlying 2‑D material [1]. Electron microscopy confirmed consistent orientation and minimal interfacial distortion, a stark contrast to conventional epitaxy that typically requires much higher temperatures and can damage temperature‑sensitive stacks [2].
Using the aligned Te films, the researchers fabricated functional transistors and optoelectronic components, demonstrating that the method is not limited to material synthesis but extends to practical device manufacturing [1]. The versatility was shown across multiple van der Waals substrates, indicating a scalable route for heterogeneous integration of diverse semiconductors on a single chip [2].
Tellurium’s anisotropic conductivity and favorable optical properties make it attractive for photodetectors, LEDs, and ultra‑low‑power electronics [1]. By enabling epitaxial growth at 150 °C, the technique supports the stacking of temperature‑sensitive layers—crucial for complex AI processors that rely on clean, atomically precise interfaces. The authors suggest the method could become a core manufacturing platform for heterogeneous semiconductor integration, potentially lowering power consumption and boosting performance in next‑generation chips [1][2].
The breakthrough shows that precise crystal alignment need not come at the cost of high‑temperature processing, opening a practical path for integrating a wide range of next‑generation semiconductor materials while preserving their intrinsic properties.
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